CY7C2165KV18 Features
* Separate independent read and write data ports
* Supports concurrent transactions
* 550-MHz clock for high bandwidth
* Four-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
CY7C2163KV18-CypressSemiconductor.pdf
Datasheet Details
CY7C2165KV18, CY7C2163KV18
Cypress Semiconductor
623.35 KB
18-mbit qdr ii+ sram four-word burst architecture.
This datasheet PDF includes multiple part numbers: CY7C2165KV18, CY7C2163KV18.
Please refer to the document for exact specifications by model.
📁 Related Datasheet
CY7C2163KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C2168KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C2170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C2245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C225 512 x 8 Registered PROM (Cypress)
CY7C225A 512 x 8 Registered PROM (Cypress Semiconductor)
CY7C2262XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C2263KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C2165KV18 Distributor
