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CY7C2168KV18 - 18-Mbit DDR II+ SRAM Two-Word Burst Architecture

Cypress Semiconductor

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Datasheet Details

Part number: CY7C2168KV18
Manufacturer: Cypress Semiconductor
File Size: 624.09 KB
Datasheet: CY7C2168KV18-CypressSemiconductor.pdf
Description: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture

CY7C2168KV18 Product details

Features

18-Mbit density (1M × 18, 512K × 36).
550-MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed systems.
Data valid pin (QVLD) to indicate valid data on the output.
On.

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18-Mbit DDR II + SRAM Two-Word Burst Architecture Cypress Semiconductor

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CY7C2168KV18 Stock/Price