Two-Word Datasheet | Specifications & PDF Download

CY7C2670KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2

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2001.May Rev.0.1 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5Y5

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CY7C2642KV18/CY7C2644KV18 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 144-Mbit QDR® II+ SRAM Two-Word Burst

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CY7C1168KV18/CY7C1170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 18-Mbit DDR II+ SRAM Two-Word Burst Architecture

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CY7C1168KV18/CY7C1170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 18-Mbit DDR II+ SRAM Two-Word Burst Architecture

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CY7C1668KV18 CY7C1670KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 144-Mbit DDR II+ SRAM Two-Word Burst Architectur

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CY7C2268KV18/CY7C2270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit DDR II+ SRAM Two-Word Burst Arch

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CY7C2268KV18/CY7C2270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit DDR II+ SRAM Two-Word Burst Arch

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CY7C1518KV18 CY7C1520KV18 72-Mbit DDR-II SRAM Two-Word Burst Architecture 72-Mbit DDR-II SRAM Two-Word Burst Architecture Features ■ 72-Mbit density

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CYRS1542AV18 CYRS1544AV18 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture with RadStop™ Technology 72-Mbit QDR® II+ SRAM Two-Word Burst Architectur

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CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 36-Mbit QDR® II SRAM Two-Word Burst Architecture 36-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■ S

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CY7C1312KV18/CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■ Separate indep

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CY7C2262XV18/CY7C2264XV18 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ Xtreme SRAM Two

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CY7C2262XV18/CY7C2264XV18 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ Xtreme SRAM Two

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CY7C1268KV18/CY7C1270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit DDR II+ SRAM Two-Word Burst Architecture

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2001.June Rev.0.0 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5

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2001.May Rev.0.1 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5Y5

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Preliminary Notice: This is not final specification. Some parametric limits are subject to change. DESCRIPTION The M5M5T5672TG is a family of 18M bit

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HN58X2408I/HN58X2416I HN58X2432I/HN58X2464I Two-wire serial interface 8k EEPROM (1-kword × 8-bit)/16k EEPROM (2-kword × 8-bit) 32k EEPROM (4-kword × 8

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