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CY7C1250KV18 - 36-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C1248KV18/CY7C1250KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit DDR II+ SRAM Two-Word Burst Architecture .CY7C1614KV18 - 144-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1625KV18 CY7C1612KV18 CY7C1614KV18 144-Mbit QDR® II SRAM Two-Word Burst Architecture 144-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■.CY7C1314KV18 - 18-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1312KV18/CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■ Separate indep.CY7C1270KV18 - 36-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C1268KV18/CY7C1270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit DDR II+ SRAM Two-Word Burst Architecture .CY7C1618KV18 - 144-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1618KV18/CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture 144-Mbit DDR II SRAM Two-Word Burst Architecture Features ■ 144-Mbit densi.CY7C1625KV18 - 144-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1625KV18 CY7C1612KV18 CY7C1614KV18 144-Mbit QDR® II SRAM Two-Word Burst Architecture 144-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■.CY7C1612KV18 - 144-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1625KV18 CY7C1612KV18 CY7C1614KV18 144-Mbit QDR® II SRAM Two-Word Burst Architecture 144-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■.CY7C1393KV18 - 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture
CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features ■ 18-Mbit .CY7C1423KV18 - 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture
CY7C1423KV18/CY7C1424KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features ■ 36-Mbit .HN58X2464I - Two-wire serial interface 64k EEPROM (8-kword x 8-bit)
HN58X2408I/HN58X2416I HN58X2432I/HN58X2464I Two-wire serial interface 8k EEPROM (1-kword × 8-bit)/16k EEPROM (2-kword × 8-bit) 32k EEPROM (4-kword × 8.HN58X2416I - Two-wire serial interface 16k EEPROM (2-kword x 8-bit)
HN58X2408I/HN58X2416I HN58X2432I/HN58X2464I Two-wire serial interface 8k EEPROM (1-kword × 8-bit)/16k EEPROM (2-kword × 8-bit) 32k EEPROM (4-kword × 8.CY7C25422KV18 - 72-Mbit QDR II+ SRAM Two-Word Burst Architecture
CY7C25422KV18 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (.CY7C2642KV18 - 144-Mbit QDR II+ SRAM Two-Word Burst Architecture
CY7C2642KV18/CY7C2644KV18 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 144-Mbit QDR® II+ SRAM Two-Word Burst .CY7C1425KV18 - 36-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 36-Mbit QDR® II SRAM Two-Word Burst Architecture 36-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■ S.CY7C1312KV18 - 18-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1312KV18/CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■ Separate indep.CY7C2262XV18 - 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C2262XV18/CY7C2264XV18 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ Xtreme SRAM Two.CY7C2264XV18 - 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C2262XV18/CY7C2264XV18 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ Xtreme SRAM Two.CY7C2562XV18 - 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
.CY7C1168KV18 - 18-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C1168KV18/CY7C1170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 18-Mbit DDR II+ SRAM Two-Word Burst Architecture .CY7C1268KV18 - 36-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C1268KV18/CY7C1270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit DDR II+ SRAM Two-Word Burst Architecture .