CY7C1414KV18

36-Mbit QDR II SRAM Two-Word Burst Architecture

Cypress Semiconductor

* Separate independent read and write data ports

* Supports concurrent transactions

* 333 MHz clock for high bandwidth

* Two-word burst on all accesses

* Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz

* Two input clocks

CY7C1414KV18

Cypress Semiconductor

1.26 MB

36-mbit qdr ii sram two-word burst architecture.

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