CY7C25682KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture

Cypress Semiconductor

Description

CY7C25682KV18 CY7C25702KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 72-Mbit DDR II+ SRAM Two-Word Burst Ar.

📥 Download Datasheet

CY7C25682KV18 Datasheet Preview — Preview of CY7C25682KV18 PDF

Datasheet Specifications

Part number: CY7C25682KV18
Manufacturer: Cypress Semiconductor
File Size: 604.30 KB
Datasheet: CY7C25682KV18-CypressSemiconductor.pdf
Description: 72-Mbit DDR II+ SRAM Two-Word Burst Architecture

Features

* 72-Mbit density (4M × 18, 2M × 36)
* 550 MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
* Available in 2.5 clock cycle latency
* Two input clocks (K and K) for pr

CY7C25682KV18 Distributors

📁 Related Datasheet

CY7C225 CY7C277 CY7C008 CY7C008V CY7C009 CY7C009V

📌 All Tags

CY7C25682KV18 72-Mbit DDR II + SRAM Two-Word Burst Architecture Cypress Semiconductor

Cypress Semiconductor CY7C25682KV18-like datasheet