CY7C1150KV18 Datasheet - Cypress Semiconductor

CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture

CY7C1150KV18 Features

* 18-Mbit density (1M × 18, 512K × 36)

* 450-MHz clock for high bandwidth

* Two-word burst for reducing address bus frequency

* Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz

* Available in 2.0 clock cycle latency

* Two input clocks (K and K) for p

Datasheet Details

CY7C1150KV18

Cypress Semiconductor

610.31 KB

18-mbit ddr ii+ sram two-word burst architecture.

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