CY7C1150KV18 Features
* 18-Mbit density (1M × 18, 512K × 36)
* 450-MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz
* Available in 2.0 clock cycle latency
* Two input clocks (K and K) for p
CY7C1148KV18-CypressSemiconductor.pdf
Datasheet Details
CY7C1150KV18, CY7C1148KV18
Cypress Semiconductor
610.31 KB
18-mbit ddr ii+ sram two-word burst architecture.
This datasheet PDF includes multiple part numbers: CY7C1150KV18, CY7C1148KV18.
Please refer to the document for exact specifications by model.
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CY7C1150KV18 Distributor
