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CY7C1156V18, CY7C1141V18 (CY7C11xxV18) SRAM 4-Word Burst Architecture

CY7C1156V18 Description

CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) .
The CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 are 1.

CY7C1156V18 Features

* Separate Independent read and write data ports
* Supports concurrent transactions
* 300 MHz to 375 MHz clock for high bandwidth
* 4-Word Burst for reducing address bus frequency
* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 750 MHz) at 375 MHz

📥 Download Datasheet

This datasheet PDF includes multiple part numbers: CY7C1156V18, CY7C1141V18. Please refer to the document for exact specifications by model.
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Datasheet Details

Part number
CY7C1156V18, CY7C1141V18
Manufacturer
Cypress Semiconductor
File Size
1.18 MB
Datasheet
CY7C1141V18_CypressSemiconductor.pdf
Description
(CY7C11xxV18) SRAM 4-Word Burst Architecture
Note
This datasheet PDF includes multiple part numbers: CY7C1156V18, CY7C1141V18.
Please refer to the document for exact specifications by model.

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📌 All Tags

CY7C11xxV18 SRAM 4-Word Burst Architecture Cypress Semiconductor
Cypress Semiconductor CY7C1156V18-like datasheet