CY7C1648KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture

Cypress Semiconductor

Description

CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 144-Mbit DDR II+ SRAM Two-Word Burst Architectur.

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Datasheet Specifications

Part number: CY7C1648KV18
Manufacturer: Cypress Semiconductor
File Size: 597.87 KB
Datasheet: CY7C1648KV18-CypressSemiconductor.pdf
Description: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture

Features

* 144-Mbit density (8 M × 18, 4 M × 36)
* 450-MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz
* Available in 2.0-clock cycle latency
* Two input clocks (K and K) for

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CY7C1648KV18 144-Mbit DDR II + SRAM Two-Word Burst Architecture Cypress Semiconductor

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