CY7C1612KV18 Datasheet - Cypress Semiconductor

144-Mbit QDR II SRAM Two-Word Burst Architecture

* Separate independent read and write data ports

* Supports concurrent transactions

* 360-MHz clock for high bandwidth

* Two-word burst on all accesses

* Double data rate (DDR) interfaces on both read and write ports (data transferred at 720 MHz) at 360 MHz

* Two input clocks

CY7C1612KV18

Cypress Semiconductor

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144-mbit qdr ii sram two-word burst architecture.

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