CY7C1614KV18 Features
* Separate independent read and write data ports
* Supports concurrent transactions
* 360-MHz clock for high bandwidth
* Two-word burst on all accesses
* Double data rate (DDR) interfaces on both read and write ports (data transferred at 720 MHz) at 360 MHz
* Two input clocks
CY7C1625KV18-CypressSemiconductor.pdf
Datasheet Details
CY7C1614KV18, CY7C1625KV18
Cypress Semiconductor
593.44 KB
144-mbit qdr ii sram two-word burst architecture.
This datasheet PDF includes multiple part numbers: CY7C1614KV18, CY7C1625KV18.
Please refer to the document for exact specifications by model.
CY7C1614KV18 Distributor
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