CY7C1615KV18 Features
* Separate independent read and write data ports
* Supports concurrent transactions
* 333 MHz clock for high bandwidth
* Four-word burst for reducing address bus frequency
* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
CY7C1613KV18-CypressSemiconductor.pdf
Datasheet Details
CY7C1615KV18, CY7C1613KV18
Cypress Semiconductor
586.14 KB
144-mbit qdr ii sram four-word burst architecture.
This datasheet PDF includes multiple part numbers: CY7C1615KV18, CY7C1613KV18.
Please refer to the document for exact specifications by model.
CY7C1615KV18 Distributor
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