CY7C1618KV18 Datasheet - Cypress Semiconductor

CY7C1618KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture

CY7C1618KV18 Features

* 144-Mbit density (8M × 18, 4M × 36)

* 333 MHz clock for high bandwidth

* Two-word burst for reducing address bus frequency

* Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz

* Two input clocks (K and K) for precise DDR timing

* SRAM uses rising edg

Datasheet Details

CY7C1618KV18

Cypress Semiconductor

569.14 KB

144-mbit ddr ii sram two-word burst architecture.

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