CY7C1620KV18 Features
* 144-Mbit density (8M × 18, 4M × 36)
* 333 MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
* Two input clocks (K and K) for precise DDR timing
* SRAM uses rising edg
CY7C1618KV18-CypressSemiconductor.pdf
Datasheet Details
CY7C1620KV18, CY7C1618KV18
Cypress Semiconductor
569.14 KB
144-mbit ddr ii sram two-word burst architecture.
This datasheet PDF includes multiple part numbers: CY7C1620KV18, CY7C1618KV18.
Please refer to the document for exact specifications by model.
CY7C1620KV18 Distributor
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