CY7C1613KV18 Datasheet - Cypress Semiconductor

144-Mbit QDR II SRAM Four-Word Burst Architecture

* Separate independent read and write data ports

* Supports concurrent transactions

* 333 MHz clock for high bandwidth

* Four-word burst for reducing address bus frequency

* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz

CY7C1613KV18

Cypress Semiconductor

586.14 KB

144-mbit qdr ii sram four-word burst architecture.

📁 Related Datasheet

CY7C1612KV18 144-Mbit QDR II SRAM Two-Word Burst Architecture (Cypress Semiconductor)

CY7C1614KV18 144-Mbit QDR II SRAM Two-Word Burst Architecture (Cypress Semiconductor)

CY7C1615KV18 144-Mbit QDR II SRAM Four-Word Burst Architecture (Cypress Semiconductor)

CY7C1618KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture (Cypress Semiconductor)

CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture (Cypress Semiconductor)

CY7C1625KV18 144-Mbit QDR II SRAM Two-Word Burst Architecture (Cypress Semiconductor)

CY7C164 16K x 4 Static RAM (Cypress Semiconductor)

CY7C1643KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)

CY7C1645KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)

CY7C1648KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (Cypress Semiconductor)

TAGS

Image Gallery