CY7C1613KV18 Datasheet - Cypress Semiconductor

CY7C1613KV18 144-Mbit QDR II SRAM Four-Word Burst Architecture

CY7C1613KV18 Features

* Separate independent read and write data ports

* Supports concurrent transactions

* 333 MHz clock for high bandwidth

* Four-word burst for reducing address bus frequency

* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz

Datasheet Details

CY7C1613KV18

Cypress Semiconductor

586.14 KB

144-mbit qdr ii sram four-word burst architecture.

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