* Separate independent read and write data ports
* Supports concurrent transactions
* 450 MHz clock for high bandwidth
* 2-word burst for reducing address bus frequency
* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
CY7C2264XV18 Datasheet (647.92 KB)
CY7C2264XV18
Cypress Semiconductor
647.92 KB
36-mbit qdr ii+ xtreme sram two-word burst architecture.
CY7C2262XV18/CY7C2264XV18
36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
36-Mbit QDR® II+ Xtreme SRAM Two.
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