* Separate independent read and write data ports
* Supports concurrent transactions
* 633 MHz clock for high bandwidth
* Four-word burst for reducing address bus frequency
* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1266 MHz) at 633 MHz
CY7C2265XV18 Datasheet (1.07 MB)
CY7C2265XV18
Cypress Semiconductor
1.07 MB
36-mbit qdr ii+ xtreme sram four-word burst architecture.
CY7C2263XV18 CY7C2265XV18
36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
36-Mbit QDR® II+ Xtreme SRAM Fo.
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