CY7C2265XV18 Datasheet - Cypress Semiconductor

CY7C2265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture

CY7C2265XV18 Features

* Separate independent read and write data ports

* Supports concurrent transactions

* 633 MHz clock for high bandwidth

* Four-word burst for reducing address bus frequency

* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1266 MHz) at 633 MHz

Datasheet Details

CY7C2265XV18

Cypress Semiconductor

1.07 MB

36-mbit qdr ii+ xtreme sram four-word burst architecture.

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TAGS

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