CY7C2265XV18 Datasheet, architecture equivalent, Cypress Semiconductor

CY7C2265XV18 Features

• Architecture
• Separate independent read and write data ports
• Supports concurrent transactions
• 633 MHz clock for high bandwidth
• Four-word burst for reducing add

PDF File Details

Part number:

CY7C2265XV18

Manufacturer:

Cypress Semiconductor

File Size:

1.07MB

Download:

📄 Datasheet

Description:

36-mbit qdr ii+ xtreme sram four-word burst architecture.

TAGS

CY7C2265XV18

Cypress Semiconductor

📁 Related Datasheet

CY7C2265KV18 - 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C2263KV18/CY7C2265KV18 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Arc.

CY7C2262XV18 - 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C2262XV18/CY7C2264XV18 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ Xtreme SRAM Two.

CY7C2263KV18 - 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C2263KV18/CY7C2265KV18 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Arc.

CY7C2263XV18 - 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C2263XV18 CY7C2265XV18 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ Xtreme SRAM Fo.

CY7C2264XV18 - 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C2262XV18/CY7C2264XV18 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ Xtreme SRAM Two.

CY7C2268KV18 - 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C2268KV18/CY7C2270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit DDR II+ SRAM Two-Word Burst Arch.

CY7C2245KV18 - 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C2245KV18 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture .

CY7C225 - 512 x 8 Registered PROM (Cypress)
.

CY7C225A - 512 x 8 Registered PROM (Cypress Semiconductor)
1CY7C225A CY7C225A 512 x 8 Registered PROM Features • CMOS for optimum speed/power • High speed — 25 ns address set-up — 12 ns clock to output • Lo.

CY7C2270KV18 - 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C2268KV18/CY7C2270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit DDR II+ SRAM Two-Word Burst Arch.