* Separate independent read and write data ports
* Supports concurrent transactions
* 550 MHz clock for high bandwidth
* Four-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MH
CY7C2263KV18 Datasheet (631.21 KB)
CY7C2263KV18
Cypress Semiconductor
631.21 KB
36-mbit qdr ii+ sram four-word burst architecture.
CY7C2263KV18/CY7C2265KV18
36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
36-Mbit QDR® II+ SRAM 4-Word Burst Arc.
📁 Related Datasheet
CY7C2263XV18 - 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
(Cypress Semiconductor)
CY7C2263XV18 CY7C2265XV18
36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
36-Mbit QDR® II+ Xtreme SRAM Fo.
CY7C2262XV18 - 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
(Cypress Semiconductor)
CY7C2262XV18/CY7C2264XV18
36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
36-Mbit QDR® II+ Xtreme SRAM Two.
CY7C2264XV18 - 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
(Cypress Semiconductor)
CY7C2262XV18/CY7C2264XV18
36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
36-Mbit QDR® II+ Xtreme SRAM Two.
CY7C2265KV18 - 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
(Cypress Semiconductor)
CY7C2263KV18/CY7C2265KV18
36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
36-Mbit QDR® II+ SRAM 4-Word Burst Arc.
CY7C2265XV18 - 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
(Cypress Semiconductor)
CY7C2263XV18 CY7C2265XV18
36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
36-Mbit QDR® II+ Xtreme SRAM Fo.
CY7C2268KV18 - 36-Mbit DDR II+ SRAM Two-Word Burst Architecture
(Cypress Semiconductor)
CY7C2268KV18/CY7C2270KV18
36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
36-Mbit DDR II+ SRAM Two-Word Burst Arch.
CY7C2245KV18 - 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
(Cypress Semiconductor)
CY7C2245KV18
36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
36-Mbit QDR® II+ SRAM Four-Word Burst Architecture .
CY7C225 - 512 x 8 Registered PROM
(Cypress)
.
TAGS
Image Gallery
