CY7C2265KV18 Datasheet - Cypress Semiconductor

CY7C2265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture

CY7C2265KV18 Features

* Separate independent read and write data ports

* Supports concurrent transactions

* 550 MHz clock for high bandwidth

* Four-word burst for reducing address bus frequency

* Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MH

Datasheet Details

CY7C2265KV18

Cypress Semiconductor

631.21 KB

36-mbit qdr ii+ sram four-word burst architecture.

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TAGS

CY7C2265KV18 Distributor