* 36-Mbit density (2 M × 18, 1 M × 36)
* 550 MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
* Available in 2.5 clock cycle latency
* Two input clocks (K and K) for
CY7C2268KV18 Datasheet (625.92 KB)
CY7C2268KV18
Cypress Semiconductor
625.92 KB
36-mbit ddr ii+ sram two-word burst architecture.
CY7C2268KV18/CY7C2270KV18
36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
36-Mbit DDR II+ SRAM Two-Word Burst Arch.
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