* Separate independent read and write data ports
* Supports concurrent transactions
* 450 MHz clock for high bandwidth
* Four-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
CY7C2245KV18 Datasheet (1.18 MB)
CY7C2245KV18
Cypress Semiconductor
1.18 MB
36-mbit qdr ii+ sram four-word burst architecture.
CY7C2245KV18
36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
36-Mbit QDR® II+ SRAM Four-Word Burst Architecture .
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