CY7C2170KV18 - 18-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C2170KV18 Features
* 18-Mbit density (1M × 18, 512K × 36)
* 550-MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
* Available in 2.5 clock cycle latency
* Two input clocks (K and K) for
