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CY7C2170KV18

18-Mbit DDR II+ SRAM Two-Word Burst Architecture

CY7C2170KV18 Features

* 18-Mbit density (1M × 18, 512K × 36)

* 550-MHz clock for high bandwidth

* Two-word burst for reducing address bus frequency

* Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz

* Available in 2.5 clock cycle latency

* Two input clocks (K and K) for

CY7C2170KV18 Datasheet (624.09 KB)

Preview of CY7C2170KV18 PDF

Datasheet Details

Part number:

CY7C2170KV18

Manufacturer:

Cypress Semiconductor

File Size:

624.09 KB

Description:

18-mbit ddr ii+ sram two-word burst architecture.
CY7C2168KV18/CY7C2170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 18-Mbit DDR II+ SRAM Two-Word Burst Arch.

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CY7C2170KV18 18-Mbit DDR II + SRAM Two-Word Burst Architecture Cypress Semiconductor

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