CY7C2665KV18 Features
* Separate independent read and write data ports
* Supports concurrent transactions
* 550-MHz clock for high bandwidth
* Four-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
CY7C2663KV18-CypressSemiconductor.pdf
Datasheet Details
CY7C2665KV18, CY7C2663KV18
Cypress Semiconductor
1.20 MB
144-mbit qdr ii+ sram four-word burst architecture.
This datasheet PDF includes multiple part numbers: CY7C2665KV18, CY7C2663KV18.
Please refer to the document for exact specifications by model.
📁 Related Datasheet
CY7C266 8Kx8 Power-Switched and Reprogrammable PROM (Cypress Semiconductor)
CY7C2663KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C261 8K x 8 Power-Switched and Reprogrammable PROM (Cypress Semiconductor)
CY7C263 8K x 8 Power-Switched and Reprogrammable PROM (Cypress Semiconductor)
CY7C264 8K x 8 Power-Switched and Reprogrammable PROM (Cypress Semiconductor)
CY7C2642KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C265 8K x 8 Registered PROM (Cypress Semiconductor)
CY7C2665KV18 Distributor
