CY23S08 Datasheet - Cypress

CY23S08 - 3.3V Zero Delay Buffer

The CY23S08 is a 3.3 V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driven into the FBK pin, and o.

CY23S08 Features

* Zero input output propagation delay, adjustable by capacitive load on FBK input

* Multiple configurations (see Available CY23S08 Configurations on page 4)

* Multiple low-skew outputs

* 45 ps typical output-output skew (-1)

* Two banks of four outputs that can be tristated by tw

CY23S08-Cypress.pdf