DFPSQRT - Floating Point Pipelined Square Root Unit

Product Overview

Digital Core Design

Datasheet Details

Part number	DFPSQRT
Manufacturer	Digital Core Design
File Size	178.99 KB
Description	Floating Point Pipelined Square Root Unit
Datasheet	DFPSQRT Datasheet
Additional preview pages of the DFPSQRT datasheet.

Product details

Description

PIN clk rst en datai[31:0] datao[31:0] ofo ufo ifo TYPE Input Input Input Input DESCRIPTION Global system clock Global system reset Enable computing Data bus input Output Data bus output Output Overflow flag Output Underflow flag Output Invalid result flag All trademarks mentioned in this document are trademarks of their respective owners.http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD Digital Core Design.

Features

Full IEEE-754 compliance Single precision real format support Simple interface No programming required 9 levels pipelining 24-bit accuracy, 6 fractional decimal digits Results available at every clock Fully configurable Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support.

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Other Datasheets by Digital Core Design

DFP2INT - Floating Point To Integer Pipelined Converter
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DFPAU - Floating Point Arithmetic Coprocessor
DFPAU-DP - Floating Point Arithmetic Coprocessor Double Precision
DFPCOMP - Floating Point Comparator Unit
DFPDIV - Floating Point Pipelined Divider Unit

Published: Nov 9, 2008 |