DFPSQRT Datasheet - Digital Core Design

DFPSQRT, Floating Point Pipelined Square Root Unit

DFPSQRT www.DataSheet4U.com Floating Point Pipelined Square Root Unit ver 2.90 OVERVIEW * Fully synthesizable, static synchronous design with.
PIN clk rst en datai[31:0] datao[31:0] ofo ufo ifo TYPE Input Input Input Input DESCRIPTION Global system clock Global system reset Enable computing.

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DFPSQRT_DigitalCoreDesign.pdf

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Datasheet Details

Part number:

DFPSQRT

Manufacturer:

Digital Core Design

File Size:

178.99 KB

Description:

Floating Point Pipelined Square Root Unit

Features

* Full IEEE-754 compliance Single precision real format support Simple interface No programming required 9 levels pipelining 24-bit accuracy, 6 fractional decimal digits Results available at every clock Fully configurable Delivery the IP Core updates, m

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DFPSQRT Floating Point Pipelined Square Root Unit Digital Core Design

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