DFPSQRT Datasheet - Digital Core Design

DFPSQRT Floating Point Pipelined Square Root Unit

PIN clk rst en datai[31:0] datao[31:0] ofo ufo ifo TYPE Input Input Input Input DESCRIPTION Global system clock Global system reset Enable computing Data bus input Output Data bus output Output Overflow flag Output Underflow flag Output Invalid result flag All trademarks mentioned in this docume.

DFPSQRT www.DataSheet4U.com Floating Point Pipelined Square Root Unit ver 2.90 OVERVIEW Fully synthesizable, static synchronous design with no internal tri-states The DFPSQRT uses the pipelined mathematics algorithm to compute square root function. The input number format is according to IEEE-754 standard. DFPSQRT supports single precision real numbers. SQRT operation can be pipelined up to 9 levels. Input data are fed every clock cycle. The first result appears after 9 clock periods.

DFPSQRT Features

* Full IEEE-754 compliance Single precision real format support Simple interface No programming required 9 levels pipelining 24-bit accuracy, 6 fractional decimal digits Results available at every clock Fully configurable Delivery the IP Core updates, m

DFPSQRT_DigitalCoreDesign.pdf