74AUP2G00 - DUAL NAND GATE

Product Overview

Diodes

Datasheet Details

Part number	74AUP2G00
Manufacturer	DIODES
File Size	243.78 KB
Description	DUAL NAND GATE
Datasheet	74AUP2G00 Datasheet
Additional preview pages of the 74AUP2G00 datasheet.

Product details

Description

Pin Assignments The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications.The 74AUP2G00 is a dual two input NAND gate.Both gates have push-pull outputs designed for operation over a power supply range of 0.8V to 3.6V.The device is fully specified for partial power down applications using IOFF.The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down.Each gate performs

Features

Advanced Ultra Low Power (AUP) CMOS.
Supply Voltage Range from 0.8V to 3.6V.
±4mA Output Drive at 3.0V.
Low Static Power Consumption ICC < 0.9µA.
Low Dynamic Power Consumption CPD = 6 pF (Typical at 3.6V).
Schmitt Trigger Action at all inputs makes the circuit tolerant for slower input rise and fall time. The hysteresis is typically 250 mV at VCC = 3.0V.
IOFF Supports Partial-Power-Down Mode Operation.
ESD Protection Exceed.

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Published: Jul 26, 2015 |