M15T1G1664A-DEBG2C, M15T1G1664A - DDR3 SDRAM

ESMT

Datasheet Details

Part number	M15T1G1664A-DEBG2C, M15T1G1664A
Manufacturer	ESMT
File Size	7.20 MB
Description	DDR3 SDRAM
Datasheet	M15T1G1664A-ESMT.pdf
Note	This datasheet PDF includes multiple part numbers: M15T1G1664A-DEBG2C, M15T1G1664A. Please refer to the document for exact specifications by model.

The 1Gb Double-Data-Rate-3(L), DDR3(L) DRAM is double data rate architecture to achieve high-speed operation.

and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion. These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages. DDR3(L) SDRAM Addressing Configuration M15T1G1664A # of Bank 8 Bank Address BA0.

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Published: Oct 22, 2024 |