M15T1G1664A-DEBG2CS Datasheet - ESMT

DDR3 SDRAM

M15T1G1664A-DEBG2CS Features

* and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion. These de

M15T1G1664A-DEBG2CS General Description

The 1Gb Double-Data-Rate-3(L), DDR3(L) DRAM is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM. The 1Gb chip is organized as 8Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates.

M15T1G1664A-DEBG2CS Datasheet (7.20 MB)