* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EDE1116AJBG-8E-F Datasheet (537.89 KB)
EDE1116AJBG-8E-F
Elpida Memory
537.89 KB
1g bits ddr2 sdram.
DATA SHEET 1G bits DDR2 SDRAM EDE1108AJBG (128M words × 8 bits) EDE1116AJBG (64M words × 16 bits) Specifications Density: 1G bits .
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