FDC6321C Datasheet - Fairchild Semiconductor

FDC6321C Dual N & P Channel / Digital FET

These dual N & P Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low volta.

FDC6321C Features

* N-Ch 25 V, 0.68 A, RDS(ON) = 0.45 Ω @ VGS= 4.5 V P-Ch -25 V, -0.46 A, RDS(ON) = 1.1 Ω @ VGS= -4.5 V. Very low level gate drive requirements allowing direct operation in 3 V circuits. VGS(th) < 1.0V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Replace multiple dual NPN & PNP digital t

FDC6321C Datasheet (273.20 KB)