GD5F1GQ4UCFIG - SPI(x1/x2/x4) NAND Flash
5 2.1 PRODUCT LIST 5 2.2 CONNECTION DIAGRAM 6 2.3 PIN DESCRIPTION 6 2.4 BLOCK DIAGRAM 7 3 ARRAY ORGANIZATION 8 4 MEMORY MAPPING9 5 DEVICE OPERATION 10 5.1 SPI MODES 10 5.2 HOLD MODE 11 5.3 WRITE PROTECTION 11 6 COMMANDS DESCRIPTION12 7 WRITE OPERATIONS 13 7.1 WRITE ENABLE (WREN) (06H) 13 7.2
GD5F1GQ4UCFIG Features
* (0FH) AND SET FEATURES (1FH) 14 9 READ OPERATIONS16 9.1 PAGE READ 16 9.2 PAGE READ TO CACHE (13H) 16 9.3 READ FROM CACHE (03H) 17 9.4 FAST READ FROM CACHE (0BH) 17 9.5 READ FROM CACHE X2 (3BH) 18 9.6 READ FROM CACHE X4 (6BH) 18 9.7 READ FROM CACHE DUAL IO (BBH) 19 9.8 READ FROM CACHE QUAD IO (EBH
