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H55S2532JFR-A3M, H55S2622JFR-60M Datasheet - Hynix Semiconductor

H55S2532JFR-A3M 256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Nov. 2008 1 11256Mbit (8Mx32bit) Mobile SDR www.DataSheet4U.com H55S2622JFR Series H55S2532JFR Series Document Title 4Bank x 2M x 32bits Synchr.

H55S2532JFR-A3M Features

* Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK)

* MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - Duri

H55S2622JFR-60M_HynixSemiconductor.pdf

This datasheet PDF includes multiple part numbers: H55S2532JFR-A3M, H55S2622JFR-60M. Please refer to the document for exact specifications by model.
H55S2532JFR-A3M Datasheet Preview Page 2 H55S2532JFR-A3M Datasheet Preview Page 3

Datasheet Details

Part number:

H55S2532JFR-A3M, H55S2622JFR-60M

Manufacturer:

Hynix Semiconductor

File Size:

1.25 MB

Description:

256mbit mobile sdr sdrams based on 2m x 4bank x32 i/o.

Note:

This datasheet PDF includes multiple part numbers: H55S2532JFR-A3M, H55S2622JFR-60M.
Please refer to the document for exact specifications by model.

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TAGS

H55S2532JFR-A3M H55S2622JFR-60M 256MBit MOBILE SDR SDRAMs based 4Bank x32 Hynix Semiconductor

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