H55S2532JFR-75M - 256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O
and is subject to change without notice.
Hynix does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev 1.0 / Nov.
2008 1 11256Mbit (8Mx32bit) Mobile SDR www.DataSheet4U.com H55S2622JFR Series H55S2532JFR Series Document Title 4Bank x 2M x 32bits Synchr
H55S2532JFR-75M Features
* Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK)
* MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - Duri
