* Standard SDRAM Protocol Internal 4bank operation Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface Low Voltage interface to reduce I/O power 8,192 Refresh cycles / 64ms Programmable CAS latency of 2 or
H57V2562GTR Datasheet (273.59 KB)
H57V2562GTR
Hynix Semiconductor
273.59 KB
256mb synchronous dram based on 4m x 4bank x16 i/o.
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256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
256M (16Mx16bit) Hynix SDRAM Memory
Memory Cell Array
- Organized as 4banks .
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