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H57V2562GTR - 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O

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Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • Standard SDRAM Protocol Internal 4bank operation Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface Low Voltage interface to reduce I/O power 8,192 Refresh cycles / 64ms Programmable CAS latency of 2 or 3 Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst Commercial Temp : 0oC ~ 70oC Operation Package Type : 54_Pin TSOPII This p.

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Datasheet Details

Part number H57V2562GTR
Manufacturer Hynix Semiconductor
File Size 273.59 KB
Description 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
Datasheet download datasheet H57V2562GTR Datasheet
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www.DataSheet4U.com 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O 256M (16Mx16bit) Hynix SDRAM Memory Memory Cell Array - Organized as 4banks of 4,194,304 x 16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Aug. 2009 1 www.DataSheet4U.com 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series H57V2562GTR Document Title 256Mbit (16M x16) Synchronous DRAM Revision History Revision No. 0.1 1.0 History Preliminary Release Draft Date Jun. 2009 Aug. 2009 Remark Rev 1.0 / Aug. 2009 2 www.DataSheet4U.
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