H57V2562GTR Datasheet (Hynix Semiconductor) - 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O

H57V2562GTR, 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Rev 1.0 / Aug.

2009 1 www.DataSheet4U.com 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series H57V2562GTR Document Title 256Mbit (16M x16) Synchron

H57V2562GTR Features

* Standard SDRAM Protocol Internal 4bank operation Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface Low Voltage interface to reduce I/O power 8,192 Refresh cycles / 64ms Programmable CAS latency of 2 or