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H57V2562GTR

256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O

H57V2562GTR Features

* Standard SDRAM Protocol Internal 4bank operation Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface Low Voltage interface to reduce I/O power 8,192 Refresh cycles / 64ms Programmable CAS latency of 2 or

H57V2562GTR General Description

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Aug. 2009 1 www.DataSheet4U.com 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series H57V2562GTR Document Title 256Mbit (16M x16) Synchron.

H57V2562GTR Datasheet (273.59 KB)

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Datasheet Details

Part number:

H57V2562GTR

Manufacturer:

Hynix Semiconductor

File Size:

273.59 KB

Description:

256mb synchronous dram based on 4m x 4bank x16 i/o.
www.DataSheet4U.com 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O 256M (16Mx16bit) Hynix SDRAM Memory Memory Cell Array - Organized as 4banks .

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H57V2562GTR 256Mb Synchronous DRAM based 4Bank x16 Hynix Semiconductor

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