H57V2562GTR - 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O

Hynix Semiconductor

Datasheet Details

Part number	H57V2562GTR
Manufacturer	Hynix Semiconductor
File Size	273.59 KB
Description	256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
Datasheet	H57V2562GTR_HynixSemiconductor.pdf

and is subject to change without notice.

Standard SDRAM Protocol Internal 4bank operation Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface Low Voltage interface to reduce I/O power 8,192 Refresh cycles / 64ms Programmable CAS latency of 2 or 3 Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst Commercial Temp : 0oC ~ 70oC Operation Package Type : 54_Pin TSOPII This p.

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Published: Sep 23, 2010 |