H5MS2562JFR-J3M Features
* SUMMARY
* Mobile DDR SDRAM clock cycle
* MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM) - Double data rate architecture: two data transfer per
* Mobile DDR SDRAM INTERFACE - x16 bus width - Multiple
H5MS2562JFR-HynixSemiconductor.pdf
Datasheet Details
H5MS2562JFR-J3M, H5MS2562JFR
Hynix Semiconductor
1.30 MB
Mobile ddr sdram 256mbit (16m x 16bit).
This datasheet PDF includes multiple part numbers: H5MS2562JFR-J3M, H5MS2562JFR.
Please refer to the document for exact specifications by model.
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H5MS2562JFR-J3M Distributor
