H5MS2562JFR-J3M - Mobile DDR SDRAM 256Mbit (16M x 16bit)
and is subject to change without notice.
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Rev 1.2 / July.
2009 1 256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O Document Title 256Mbit (4Bank x 4M x 16bits) MOBILE DDR SDRAM Revision Histor
H5MS2562JFR-J3M Features
* SUMMARY
* Mobile DDR SDRAM clock cycle
* MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM) - Double data rate architecture: two data transfer per
* Mobile DDR SDRAM INTERFACE - x16 bus width - Multiple
