* SUMMARY
* Mobile DDR SDRAM clock cycle
* MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM) - Double data rate architecture: two data transfer per
* Mobile DDR SDRAM INTERFACE - x16 bus width - Multiple
H5MS2562JFR-L3M Datasheet (1.30 MB)
H5MS2562JFR-L3M
Hynix Semiconductor
1.30 MB
Mobile ddr sdram 256mbit (16m x 16bit).
256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O
Specification of 256Mb (16Mx16bit) Mobile DDR SDRAM
Memory Cell Array
- Organized as 4banks of .
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