* SUMMARY
* Mobile DDR SDRAM clock cycle
* MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM) - Double data rate architecture: two data transfer per
* Mobile DDR SDRAM INTERFACE - x16 bus width - Multiple
H5MS2562JFR-K3M Datasheet (1.30 MB)
H5MS2562JFR-K3M
Hynix Semiconductor
1.30 MB
Mobile ddr sdram 256mbit (16m x 16bit).
256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O
Specification of 256Mb (16Mx16bit) Mobile DDR SDRAM
Memory Cell Array
- Organized as 4banks of .
📁 Related Datasheet
H5MS2562JFR-E3M Mobile DDR SDRAM 256Mbit (16M x 16bit) (Hynix Semiconductor)
H5MS2562JFR-J3M Mobile DDR SDRAM 256Mbit (16M x 16bit) (Hynix Semiconductor)
H5MS2562JFR-L3M Mobile DDR SDRAM 256Mbit (16M x 16bit) (Hynix Semiconductor)
H5MS2562JFR Mobile DDR SDRAM 256Mbit (16M x 16bit) (Hynix Semiconductor)
H5MS2532JFR 256Mb (8Mx32bit) Mobile DDR SDRAM (Hynix Semiconductor)
H5MS2622JFR 256Mb (8Mx32bit) Mobile DDR SDRAM (Hynix Semiconductor)
H5MS1222EFP 128Mbit MOBILE DDR SDRAM (Hynix Semiconductor)
H5MS1262EFP 128M (8Mx16bit) Mobile DDR SDRAM (Hynix Semiconductor)
H5MS1G22MFP 1Gbit MOBILE DDR SDRAM (Hynix Semiconductor)
H5MS1G32MFP 1Gbit MOBILE DDR SDRAM (Hynix Semiconductor)
