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H5MS2562JFR-K3M, H5MS2562JFR Datasheet - Hynix Semiconductor

H5MS2562JFR-K3M - Mobile DDR SDRAM 256Mbit (16M x 16bit)

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Rev 1.2 / July.

2009 1 256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O Document Title 256Mbit (4Bank x 4M x 16bits) MOBILE DDR SDRAM Revision Histor

H5MS2562JFR-K3M Features

* SUMMARY

* Mobile DDR SDRAM clock cycle

* MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM) - Double data rate architecture: two data transfer per

* Mobile DDR SDRAM INTERFACE - x16 bus width - Multiple

H5MS2562JFR-HynixSemiconductor.pdf

This datasheet PDF includes multiple part numbers: H5MS2562JFR-K3M, H5MS2562JFR. Please refer to the document for exact specifications by model.
H5MS2562JFR-K3M Datasheet Preview Page 2 H5MS2562JFR-K3M Datasheet Preview Page 3

Datasheet Details

Part number:

H5MS2562JFR-K3M, H5MS2562JFR

Manufacturer:

Hynix Semiconductor

File Size:

1.30 MB

Description:

Mobile ddr sdram 256mbit (16m x 16bit).

Note:

This datasheet PDF includes multiple part numbers: H5MS2562JFR-K3M, H5MS2562JFR.
Please refer to the document for exact specifications by model.

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