HY57V121620LT Datasheet - Hynix Semiconductor

HY57V121620LT Synchronous DRAM

The HY57V121620 is a 512-Mbit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V121620 is organized as 4banks of 8,388,608x16. HY57V121620 is offering fully synchronous operation referenced to a positive edge of the clo.

HY57V121620LT Features

* Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM Internal four banks operation

HY57V121620LT Datasheet (186.66 KB)