HY5DU12822B, HY5DU121622 Datasheet (Hynix Semiconductor)

HY5DU12822B, HY5DU121622, 512 Mb DDR SDRAM

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Rev 0.1 / May 2004 1 HY5DU12422B(L)TP HY5DU12822B(L)TP HY5DU121622B(L)TP Revision History Revision No.

0.1 History Initial Draft Draft Date

HY5DU12822B Features

* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional da