* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe
HY5DU281622AT Datasheet (376.76 KB)
HY5DU281622AT
Hynix Semiconductor
376.76 KB
(hy5du28xxxat) 3rd 128m ddr sdram.
HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T
3rd 128M DDR SDRAM
HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T
This document is a general prod.
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