* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional da
HY5DU281622T Datasheet (1.54 MB)
HY5DU281622T
Hynix Semiconductor
1.54 MB
2nd 128m ddr sdram.
HY5DU28422T HY5DU28822T HY5DU281622T 2nd 128M DDR SDRAM HY5DU28422T HY5DU28822T HY5DU281622T Revision 1.3 April 2001 Rev. 1.3 / Apr. 2001 This doc.
📁 Related Datasheet
HY5DU281622 4 Banks x 2M x 16Bit Double Data Rate SDRAM (Hyundai)
HY5DU281622AT (HY5DU28xxxAT) 3rd 128M DDR SDRAM (Hynix Semiconductor)
HY5DU281622AT-6 128M(8Mx16) DDR SDRAM (Hynix Semiconductor)
HY5DU281622DT (HY5DU28xx22D(L)T) 128Mb-S DDR SDRAM (Hynix Semiconductor)
HY5DU281622ET 128M(8Mx16) GDDR SDRAM (Hynix Semiconductor)
HY5DU281622FTP 128Mb DDR SDRAM (Hynix)
HY5DU281622LT (HY5DU28xxxAT) 3rd 128M DDR SDRAM (Hynix Semiconductor)
HY5DU281622LT (HY5DU28xx22D(L)T) 128Mb-S DDR SDRAM (Hynix Semiconductor)
HY5DU281622LT-H 4 Banks x 2M x 16Bit Double Data Rate SDRAM (Hyundai)
HY5DU281622LT-K 4 Banks x 2M x 16Bit Double Data Rate SDRAM (Hyundai)
