HY5DU281622AT-6 - 128M(8Mx16) DDR SDRAM
and is subject to change without notice.
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Rev.
0.3/May.
02 1 HY5DU281622AT-6 Revision History 1.
Revision 0.2 (Dec.
01) 1) Separated ‘Function description’ and ‘Timing diagram’ part
HY5DU281622AT-6 Features
* VDD, VDDQ = 2.5V +/- 5% All inputs and outputs are compatible with SSTL_2 interface JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface
