HY5DU283222Q Datasheet (Hynix Semiconductor)

HY5DU283222Q, 128M(4Mx32) GDDR SDRAM

and is subject to change without notice.

Hynix Electronics does not assume any responsibility for use of circuits described.

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Rev.

1.2/Oct.

02 1 HY5DU283222Q Revision History No.

History 1) Changed some AC parameters a) tAC : Changed from 0.7ns to 0.9ns b) tDQSCK : C

HY5DU283222Q Features

* VDD, VDDQ = 2.5V ± 5% All inputs and outputs are compatible with SSTL_2 interface JEDEC standard 20mm x 14mm 100pin LQFP with 0.65mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface Source s