* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional da
HY5DU56822CF Datasheet (368.07 KB)
HY5DU56822CF
Hynix Semiconductor
368.07 KB
(hy5du56xxxc(l)f) 256m ddr sdram.
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