* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional da
HY5DU56822DTP Datasheet (450.52 KB)
HY5DU56822DTP
Hynix Semiconductor
450.52 KB
(hy5du56x22dtp) 256m ddr sdram.
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HY5DU56422D(L)TP HY5DU56822D(L)TP HY5DU561622D(L)TP
256M DDR SDRAM
HY5DU56422D(L)TP HY5DU56822D(L)TP HY5DU561622D(L)TP
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