* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional da
HY5DU56822LT Datasheet (529.85 KB)
HY5DU56822LT
Hynix Semiconductor
529.85 KB
(hy5du56xx22a(l)t) 256m-s ddr sdram.
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HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T
256M-S DDR SDRAM
HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T
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