HY5DV641622AT - 64M(4Mx16) DDR SDRAM
and is subject to change without notice.
Hynix Electronics does not assume any responsibility for use of circuits described.
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Rev.
0.7/May.
02 1 HY5DV641622AT Revision History 4.
Revision 0.7 (May.
02) 1) Input leakage current changed from +/-5uA to +/-2uA 3.
Revisi
HY5DV641622AT Features
* 3.3V for VDD and 2.5V for VDDQ power supply All inputs and outputs are compatible with SSTL_2 interface JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Fully differential clock inputs (CK, /CK) operation Double
