* Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK)
* MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - Duri
HY5S5B6GLF-6 Datasheet (2.99 MB)
HY5S5B6GLF-6
Hynix Semiconductor
2.99 MB
256mbit (16mx16bit) mobile sdr memory.
256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O
Specification of 256M (16Mx16bit) Mobile SDRAM
Memory Cell Array
- Organized as 4banks of 4,19.
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