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HY5S5B6GLF-6E, HY5S5B6GLF-6 Datasheet - Hynix Semiconductor

HY5S5B6GLF-6E 256Mbit (16Mx16bit) Mobile SDR Memory

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Apr. 2006 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6GLF(P)-xE Series 11 Document Title 4Bank x 4M x 16bits Synchronous DRAM Revision His.

HY5S5B6GLF-6E Features

* Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK)

* MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - Duri

HY5S5B6GLF-6_HynixSemiconductor.pdf

This datasheet PDF includes multiple part numbers: HY5S5B6GLF-6E, HY5S5B6GLF-6. Please refer to the document for exact specifications by model.
HY5S5B6GLF-6E Datasheet Preview Page 2 HY5S5B6GLF-6E Datasheet Preview Page 3

Datasheet Details

Part number:

HY5S5B6GLF-6E, HY5S5B6GLF-6

Manufacturer:

Hynix Semiconductor

File Size:

2.99 MB

Description:

256mbit (16mx16bit) mobile sdr memory.

Note:

This datasheet PDF includes multiple part numbers: HY5S5B6GLF-6E, HY5S5B6GLF-6.
Please refer to the document for exact specifications by model.

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TAGS

HY5S5B6GLF-6E HY5S5B6GLF-6 256Mbit 16Mx16bit Mobile SDR Memory Hynix Semiconductor

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