HY5S5B6GLF-S - 256Mbit (16Mx16bit) Mobile SDR Memory
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Rev 1.0 / Apr.
2006 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6GLF(P)-xE Series 11 Document Title 4Bank x 4M x 16bits Synchronous DRAM Revision His
HY5S5B6GLF-S Features
* Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK)
* MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - Duri
