HY62U8100B Datasheet - Hynix Semiconductor

HY62U8100B 128K x8 bit 3.0V Low Power CMOS slow SRAM

and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 13 / Apr. 2001 Hynix Semiconductor HY62U8100B Series DESCRIPTION The HY62U8100B is a high speed, low power and 1M bit CMOS SRAM organized.

HY62U8100B Series 128Kx8bit CMOS SRAM Document Title 128K x8 bit 3.0V Low Power CMOS slow SRAM Revision History Revision No 10 History Initial Revision History Insert Revised - Insert 70ns Part Change the Notch Location of sTSOP - Left-Top => Left-Center Marking Information Add Revised - AC Test Condition Add : 5pF Test Load Changed Logo - HYUNDAI -> hynix - Marking Information Change Draft Date Jul.25.2000 Remark Final 11 Sep.04.2000 Final 12 Dec.04.2000 Final 13 Apr.30.2001 Final w.

HY62U8100B Features

* Fully static operation and Tri-state output

* TTL compatible inputs and outputs

* Battery backup(LL-part) -. 2.0V(min) data retention

* Standard pin configuration -. 32 - SOP - 525mil -. 32 - TSOP-I - 8X20(Standard and Reversed) -. 32 - sTSOP-I - 8X13.4 (Standard an

HY62U8100B Datasheet (193.38 KB)